
polym-02:     file format elf64-littleaarch64


Disassembly of section .init:

00000000004005e8 <_init>:
  4005e8:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4005ec:	910003fd 	mov	x29, sp
  4005f0:	9400003a 	bl	4006d8 <call_weak_fn>
  4005f4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4005f8:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400600 <.plt>:
  400600:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400604:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf418>
  400608:	f947fe11 	ldr	x17, [x16, #4088]
  40060c:	913fe210 	add	x16, x16, #0xff8
  400610:	d61f0220 	br	x17
  400614:	d503201f 	nop
  400618:	d503201f 	nop
  40061c:	d503201f 	nop

0000000000400620 <__libc_start_main@plt>:
  400620:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400624:	f9400211 	ldr	x17, [x16]
  400628:	91000210 	add	x16, x16, #0x0
  40062c:	d61f0220 	br	x17

0000000000400630 <__cxa_atexit@plt>:
  400630:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400634:	f9400611 	ldr	x17, [x16, #8]
  400638:	91002210 	add	x16, x16, #0x8
  40063c:	d61f0220 	br	x17

0000000000400640 <_ZNSt8ios_base4InitC1Ev@plt>:
  400640:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400644:	f9400a11 	ldr	x17, [x16, #16]
  400648:	91004210 	add	x16, x16, #0x10
  40064c:	d61f0220 	br	x17

0000000000400650 <abort@plt>:
  400650:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400654:	f9400e11 	ldr	x17, [x16, #24]
  400658:	91006210 	add	x16, x16, #0x18
  40065c:	d61f0220 	br	x17

0000000000400660 <__gmon_start__@plt>:
  400660:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400664:	f9401211 	ldr	x17, [x16, #32]
  400668:	91008210 	add	x16, x16, #0x20
  40066c:	d61f0220 	br	x17

0000000000400670 <printf@plt>:
  400670:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400674:	f9401611 	ldr	x17, [x16, #40]
  400678:	9100a210 	add	x16, x16, #0x28
  40067c:	d61f0220 	br	x17

0000000000400680 <_ZNSt8ios_base4InitD1Ev@plt>:
  400680:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400684:	f9401a11 	ldr	x17, [x16, #48]
  400688:	9100c210 	add	x16, x16, #0x30
  40068c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400690 <_start>:
  400690:	d280001d 	mov	x29, #0x0                   	// #0
  400694:	d280001e 	mov	x30, #0x0                   	// #0
  400698:	aa0003e5 	mov	x5, x0
  40069c:	f94003e1 	ldr	x1, [sp]
  4006a0:	910023e2 	add	x2, sp, #0x8
  4006a4:	910003e6 	mov	x6, sp
  4006a8:	580000c0 	ldr	x0, 4006c0 <_start+0x30>
  4006ac:	580000e3 	ldr	x3, 4006c8 <_start+0x38>
  4006b0:	58000104 	ldr	x4, 4006d0 <_start+0x40>
  4006b4:	97ffffdb 	bl	400620 <__libc_start_main@plt>
  4006b8:	97ffffe6 	bl	400650 <abort@plt>
  4006bc:	00000000 	.inst	0x00000000 ; undefined
  4006c0:	00400804 	.word	0x00400804
  4006c4:	00000000 	.word	0x00000000
  4006c8:	00400988 	.word	0x00400988
  4006cc:	00000000 	.word	0x00000000
  4006d0:	00400a08 	.word	0x00400a08
  4006d4:	00000000 	.word	0x00000000

00000000004006d8 <call_weak_fn>:
  4006d8:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf418>
  4006dc:	f947f000 	ldr	x0, [x0, #4064]
  4006e0:	b4000040 	cbz	x0, 4006e8 <call_weak_fn+0x10>
  4006e4:	17ffffdf 	b	400660 <__gmon_start__@plt>
  4006e8:	d65f03c0 	ret
  4006ec:	00000000 	.inst	0x00000000 ; undefined

00000000004006f0 <deregister_tm_clones>:
  4006f0:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  4006f4:	91012000 	add	x0, x0, #0x48
  4006f8:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  4006fc:	91012021 	add	x1, x1, #0x48
  400700:	eb00003f 	cmp	x1, x0
  400704:	540000a0 	b.eq	400718 <deregister_tm_clones+0x28>  // b.none
  400708:	90000001 	adrp	x1, 400000 <_init-0x5e8>
  40070c:	f9451421 	ldr	x1, [x1, #2600]
  400710:	b4000041 	cbz	x1, 400718 <deregister_tm_clones+0x28>
  400714:	d61f0020 	br	x1
  400718:	d65f03c0 	ret
  40071c:	d503201f 	nop

0000000000400720 <register_tm_clones>:
  400720:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400724:	91012000 	add	x0, x0, #0x48
  400728:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40072c:	91012021 	add	x1, x1, #0x48
  400730:	cb000021 	sub	x1, x1, x0
  400734:	9343fc21 	asr	x1, x1, #3
  400738:	8b41fc21 	add	x1, x1, x1, lsr #63
  40073c:	9341fc21 	asr	x1, x1, #1
  400740:	b40000a1 	cbz	x1, 400754 <register_tm_clones+0x34>
  400744:	90000002 	adrp	x2, 400000 <_init-0x5e8>
  400748:	f9451842 	ldr	x2, [x2, #2608]
  40074c:	b4000042 	cbz	x2, 400754 <register_tm_clones+0x34>
  400750:	d61f0040 	br	x2
  400754:	d65f03c0 	ret

0000000000400758 <__do_global_dtors_aux>:
  400758:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40075c:	910003fd 	mov	x29, sp
  400760:	f9000bf3 	str	x19, [sp, #16]
  400764:	b0000093 	adrp	x19, 411000 <__libc_start_main@GLIBC_2.17>
  400768:	39412260 	ldrb	w0, [x19, #72]
  40076c:	35000080 	cbnz	w0, 40077c <__do_global_dtors_aux+0x24>
  400770:	97ffffe0 	bl	4006f0 <deregister_tm_clones>
  400774:	52800020 	mov	w0, #0x1                   	// #1
  400778:	39012260 	strb	w0, [x19, #72]
  40077c:	f9400bf3 	ldr	x19, [sp, #16]
  400780:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400784:	d65f03c0 	ret

0000000000400788 <frame_dummy>:
  400788:	17ffffe6 	b	400720 <register_tm_clones>

000000000040078c <_Z9TestBoundv>:
  40078c:	a9ba7bfd 	stp	x29, x30, [sp, #-96]!
  400790:	910003fd 	mov	x29, sp
  400794:	910143a0 	add	x0, x29, #0x50
  400798:	94000042 	bl	4008a0 <_ZN4BaseC1Ev>
  40079c:	910103a0 	add	x0, x29, #0x40
  4007a0:	94000058 	bl	400900 <_ZN4Sub1C1Ev>
  4007a4:	9100c3a0 	add	x0, x29, #0x30
  4007a8:	94000067 	bl	400944 <_ZN4Sub2C1Ev>
  4007ac:	910143a0 	add	x0, x29, #0x50
  4007b0:	f9000fa0 	str	x0, [x29, #24]
  4007b4:	910103a0 	add	x0, x29, #0x40
  4007b8:	f90013a0 	str	x0, [x29, #32]
  4007bc:	9100c3a0 	add	x0, x29, #0x30
  4007c0:	f90017a0 	str	x0, [x29, #40]
  4007c4:	b9005fbf 	str	wzr, [x29, #92]
  4007c8:	b9405fa0 	ldr	w0, [x29, #92]
  4007cc:	7100081f 	cmp	w0, #0x2
  4007d0:	5400014c 	b.gt	4007f8 <_Z9TestBoundv+0x6c>
  4007d4:	b9805fa0 	ldrsw	x0, [x29, #92]
  4007d8:	d37df000 	lsl	x0, x0, #3
  4007dc:	910063a1 	add	x1, x29, #0x18
  4007e0:	f8606820 	ldr	x0, [x1, x0]
  4007e4:	9400003a 	bl	4008cc <_ZN4Base5printEv>
  4007e8:	b9405fa0 	ldr	w0, [x29, #92]
  4007ec:	11000400 	add	w0, w0, #0x1
  4007f0:	b9005fa0 	str	w0, [x29, #92]
  4007f4:	17fffff5 	b	4007c8 <_Z9TestBoundv+0x3c>
  4007f8:	d503201f 	nop
  4007fc:	a8c67bfd 	ldp	x29, x30, [sp], #96
  400800:	d65f03c0 	ret

0000000000400804 <main>:
  400804:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400808:	910003fd 	mov	x29, sp
  40080c:	b9001fa0 	str	w0, [x29, #28]
  400810:	f9000ba1 	str	x1, [x29, #16]
  400814:	97ffffde 	bl	40078c <_Z9TestBoundv>
  400818:	52800000 	mov	w0, #0x0                   	// #0
  40081c:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400820:	d65f03c0 	ret

0000000000400824 <_Z41__static_initialization_and_destruction_0ii>:
  400824:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400828:	910003fd 	mov	x29, sp
  40082c:	b9001fa0 	str	w0, [x29, #28]
  400830:	b9001ba1 	str	w1, [x29, #24]
  400834:	b9401fa0 	ldr	w0, [x29, #28]
  400838:	7100041f 	cmp	w0, #0x1
  40083c:	540001e1 	b.ne	400878 <_Z41__static_initialization_and_destruction_0ii+0x54>  // b.any
  400840:	b9401ba1 	ldr	w1, [x29, #24]
  400844:	529fffe0 	mov	w0, #0xffff                	// #65535
  400848:	6b00003f 	cmp	w1, w0
  40084c:	54000161 	b.ne	400878 <_Z41__static_initialization_and_destruction_0ii+0x54>  // b.any
  400850:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400854:	91014000 	add	x0, x0, #0x50
  400858:	97ffff7a 	bl	400640 <_ZNSt8ios_base4InitC1Ev@plt>
  40085c:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400860:	91010002 	add	x2, x0, #0x40
  400864:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400868:	91014001 	add	x1, x0, #0x50
  40086c:	90000000 	adrp	x0, 400000 <_init-0x5e8>
  400870:	911a0000 	add	x0, x0, #0x680
  400874:	97ffff6f 	bl	400630 <__cxa_atexit@plt>
  400878:	d503201f 	nop
  40087c:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400880:	d65f03c0 	ret

0000000000400884 <_GLOBAL__sub_I__Z9TestBoundv>:
  400884:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400888:	910003fd 	mov	x29, sp
  40088c:	529fffe1 	mov	w1, #0xffff                	// #65535
  400890:	52800020 	mov	w0, #0x1                   	// #1
  400894:	97ffffe4 	bl	400824 <_Z41__static_initialization_and_destruction_0ii>
  400898:	a8c17bfd 	ldp	x29, x30, [sp], #16
  40089c:	d65f03c0 	ret

00000000004008a0 <_ZN4BaseC1Ev>:
  4008a0:	d10043ff 	sub	sp, sp, #0x10
  4008a4:	f90007e0 	str	x0, [sp, #8]
  4008a8:	f94007e0 	ldr	x0, [sp, #8]
  4008ac:	52800021 	mov	w1, #0x1                   	// #1
  4008b0:	b9000001 	str	w1, [x0]
  4008b4:	f94007e0 	ldr	x0, [sp, #8]
  4008b8:	52800041 	mov	w1, #0x2                   	// #2
  4008bc:	b9000401 	str	w1, [x0, #4]
  4008c0:	d503201f 	nop
  4008c4:	910043ff 	add	sp, sp, #0x10
  4008c8:	d65f03c0 	ret

00000000004008cc <_ZN4Base5printEv>:
  4008cc:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4008d0:	910003fd 	mov	x29, sp
  4008d4:	f9000fa0 	str	x0, [x29, #24]
  4008d8:	f9400fa0 	ldr	x0, [x29, #24]
  4008dc:	b9400001 	ldr	w1, [x0]
  4008e0:	f9400fa0 	ldr	x0, [x29, #24]
  4008e4:	b9400402 	ldr	w2, [x0, #4]
  4008e8:	90000000 	adrp	x0, 400000 <_init-0x5e8>
  4008ec:	91290000 	add	x0, x0, #0xa40
  4008f0:	97ffff60 	bl	400670 <printf@plt>
  4008f4:	d503201f 	nop
  4008f8:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4008fc:	d65f03c0 	ret

0000000000400900 <_ZN4Sub1C1Ev>:
  400900:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400904:	910003fd 	mov	x29, sp
  400908:	f9000fa0 	str	x0, [x29, #24]
  40090c:	f9400fa0 	ldr	x0, [x29, #24]
  400910:	97ffffe4 	bl	4008a0 <_ZN4BaseC1Ev>
  400914:	f9400fa0 	ldr	x0, [x29, #24]
  400918:	52800081 	mov	w1, #0x4                   	// #4
  40091c:	b9000001 	str	w1, [x0]
  400920:	f9400fa0 	ldr	x0, [x29, #24]
  400924:	528000a1 	mov	w1, #0x5                   	// #5
  400928:	b9000401 	str	w1, [x0, #4]
  40092c:	f9400fa0 	ldr	x0, [x29, #24]
  400930:	528000c1 	mov	w1, #0x6                   	// #6
  400934:	b9000801 	str	w1, [x0, #8]
  400938:	d503201f 	nop
  40093c:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400940:	d65f03c0 	ret

0000000000400944 <_ZN4Sub2C1Ev>:
  400944:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400948:	910003fd 	mov	x29, sp
  40094c:	f9000fa0 	str	x0, [x29, #24]
  400950:	f9400fa0 	ldr	x0, [x29, #24]
  400954:	97ffffd3 	bl	4008a0 <_ZN4BaseC1Ev>
  400958:	f9400fa0 	ldr	x0, [x29, #24]
  40095c:	528000e1 	mov	w1, #0x7                   	// #7
  400960:	b9000001 	str	w1, [x0]
  400964:	f9400fa0 	ldr	x0, [x29, #24]
  400968:	52800101 	mov	w1, #0x8                   	// #8
  40096c:	b9000401 	str	w1, [x0, #4]
  400970:	f9400fa0 	ldr	x0, [x29, #24]
  400974:	52800121 	mov	w1, #0x9                   	// #9
  400978:	b9000801 	str	w1, [x0, #8]
  40097c:	d503201f 	nop
  400980:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400984:	d65f03c0 	ret

0000000000400988 <__libc_csu_init>:
  400988:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  40098c:	910003fd 	mov	x29, sp
  400990:	a901d7f4 	stp	x20, x21, [sp, #24]
  400994:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf418>
  400998:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf418>
  40099c:	9136c294 	add	x20, x20, #0xdb0
  4009a0:	913682b5 	add	x21, x21, #0xda0
  4009a4:	a902dff6 	stp	x22, x23, [sp, #40]
  4009a8:	cb150294 	sub	x20, x20, x21
  4009ac:	f9001ff8 	str	x24, [sp, #56]
  4009b0:	2a0003f6 	mov	w22, w0
  4009b4:	aa0103f7 	mov	x23, x1
  4009b8:	9343fe94 	asr	x20, x20, #3
  4009bc:	aa0203f8 	mov	x24, x2
  4009c0:	97ffff0a 	bl	4005e8 <_init>
  4009c4:	b4000194 	cbz	x20, 4009f4 <__libc_csu_init+0x6c>
  4009c8:	f9000bb3 	str	x19, [x29, #16]
  4009cc:	d2800013 	mov	x19, #0x0                   	// #0
  4009d0:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  4009d4:	aa1803e2 	mov	x2, x24
  4009d8:	aa1703e1 	mov	x1, x23
  4009dc:	2a1603e0 	mov	w0, w22
  4009e0:	91000673 	add	x19, x19, #0x1
  4009e4:	d63f0060 	blr	x3
  4009e8:	eb13029f 	cmp	x20, x19
  4009ec:	54ffff21 	b.ne	4009d0 <__libc_csu_init+0x48>  // b.any
  4009f0:	f9400bb3 	ldr	x19, [x29, #16]
  4009f4:	a941d7f4 	ldp	x20, x21, [sp, #24]
  4009f8:	a942dff6 	ldp	x22, x23, [sp, #40]
  4009fc:	f9401ff8 	ldr	x24, [sp, #56]
  400a00:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400a04:	d65f03c0 	ret

0000000000400a08 <__libc_csu_fini>:
  400a08:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400a0c <_fini>:
  400a0c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400a10:	910003fd 	mov	x29, sp
  400a14:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400a18:	d65f03c0 	ret
